Integrated circuits include many imbedded random access memories (RAMs) of many different sizes and offering different options (single, dual, multi-port). These RAMs sometimes fail in the field, even after passing manufacturing tests. For example, integrated circuits may include multiple RAMs used to buffer data flow. Failures may occur in such RAMs for both inbound and outbound data flow. The failures may occur intermittently depending on data pattern and voltages. Once failure occurs, it is difficult to determined the contents of the failing RAMs because the RAMs are imbedded within the integrated circuit. Failing bits and addresses thus must be inferred by examining actual data flow and working backwards to determine what would reasonably have been expected to have gone through the failing RAM. However, many uncertainties can be left in this type of analysis. Furthermore, this form of analysis consumes an inordinate amount of time.
When RAMs fail in the field, there are no readily available options to diagnose the failures as they occur. The imbedded RAMs are usually tested by imbedded built-in self-test (BIST) circuits which are small logic blocks that run a variety of tests (checkerboard, walking ones/zeros, etc.). Sometimes, the RAMs are tested through external testers, although this is not as effective due to lower pattern coverage and slower speed resulting in longer test durations. However, once in the field, a failure cannot be diagnosed through an external tester. Further, a BIST is limited in its ability to detect or diagnose failures. While a BIST may detect most failures during manufacturing, no BIST will have tests comprehensive enough to detect all possible failure modes. The reason for this is that a field failure mode will often be undetectable by BIST algorithms.
An example is when a RAM, imbedded in an integrated circuit, experiences a parity error in a data stream. It is often quite difficult to disengage the RAM from the data flow to determine exactly what section or portion of the RAM failed. BIST blocks only go through a predetermined sequence of write and read commands to test RAMs with specific data patterns. A BIST block cannot easily read the exact content of a failing RAM without going through its predetermined sequence.
Hence, there is a need in the art for a means by which RAM failures may be readily diagnosed immediately after failure occurs, even while the integrated circuit is engaged in processing data flows in the field. One or more embodiments of the present invention address such needs.